Brands |
N/A Greenray |
Package |
N/A Ceramic + Metal Lid |
Typical Aging for 10 Years |
N/A ±4 ppm |
Typical Frequency Stability (±) at -40 to +85 Degrees Celsius (ºC) Temperature1 | N/A 0.5 ppm1.0 ppm |
Typical Frequency Stability (±) at -55 to +85 Degrees Celsius (ºC) Temperature |
N/A 2.0 ppm |
Maximum Acceleration Sensitivity2 | N/A 0.7 ppb/g2.5 ppb/g |
Typical Aging Per Year |
N/A ±0.5 ppm |
Maximum Aging Per Year |
N/A ±1 ppm |
Typical Frequency Stability (±) at-55 to +95 Degrees Celsius (ºC) Temperature |
N/A 3.0 ppm |
Maximum Frequency Versus Voltage for a 2 Percent (%) Change (±) |
N/A 0.3 ppm |
Maximum Rise/Fall Time |
N/A 4 ns |
Minimum Level at 15 Power Factor (pF) Load |
N/A VDD-0.3 "1" Level |
Maximum Level at 15 Power Factor (pF) Load |
N/A 0.3 "0" Level |
Minimum Nominal Frequency |
N/A 0.75 MHz10 MHz20 MHz |
Maximum Nominal Frequency |
N/A 150 MHz50 MHz800 MHz |
Maximum Aging for 10 Years |
N/A ±6 ppm |
Maximum Aging for 20 Years |
N/A ±10 ppm |
Typical Rise/Fall Time |
N/A 2.4 ns |
Typical Rise/Fall Time for Low-Voltage Differential Signaling (LVDS) |
N/A 0.8 ns |
Maximum Rise/Fall Time for Low-Voltage Differential Signaling (LVDS) |
N/A 1.5 ns |
Maximum Rise/Fall Time for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A 0.7 ns |
Minimum Symmetry |
N/A 45 % |
Typical Symmetry |
N/A 50 % |
Maximum Symmetry |
N/A 55 % |
Typical Load at Complementary Metal-Oxide-Semiconductor (CMOS) |
N/A 15 pF |
Minimum Output Voltage3 | N/A 0.3 Vpp |
Typical Output Voltage4 | N/A 10 Vpp |
Minimum Differential Output Voltage5 | N/A 250 mV |
Typical Differential Output Voltage |
N/A 350 mV |
Maximum Differential Output Voltage |
N/A 450 mV |
Minimum Symmetry for Low-Voltage Differential Signaling (LVDS) |
N/A 45 % |
Typical Symmetry for Low-Voltage Differential Signaling (LVDS) |
N/A 50 % |
Maximum Symmetry for Low-Voltage Differential Signaling (LVDS) |
N/A 55 % |
Minimum Output Voltage for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A VDD-1.025 "1" level V |
Maximum Output Voltage for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A VDD-1.620 "0" level V |
Minimum Symmetry for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A 45 % |
Typical Symmetry for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A 50 % |
Maximum Symmetry for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A 55 % |
Minimum Direct Current (DC) Supply Voltage Drain to Drain (VDD) at ± 5% |
N/A 2.7 V4.75 V |
Typical Direct Current (DC) Supply Voltage Drain to Drain (VDD) at ± 5% |
N/A 3.3 V5.0 V |
Maximum Direct Current (DC) Supply Voltage Drain to Drain (VDD) at ± 5% |
N/A 3.6 V5.25 V |
Note for Supply Voltage |
N/A +5.0V supply is only available for CS and CL outputs from 10 MHz to 50 MHz |
Maximum Supply Current at Complementary Metal-Oxide-Semiconductor (CMOS) and Clipped Sine |
N/A 6 mA |
Maximum Supply Current at Complementary Metal-Oxide-Semiconductor (CMOS) and 750 Kilohertz (KHz) to 150 Megahertz (MHz) Frequency |
N/A 45 mA |
Maximum Supply Current for Low-Voltage Differential Signaling (LVDS) |
N/A 65 mA |
Maximum Supply Current for Low-Voltage Positive/Pseudo Emitter-Coupled Logic (LVPECL) |
N/A 80 mA |
Minimum Offset Voltage for Low-Voltage Differential Signaling (LVDS) |
N/A 1.125 V |
Typical Offset Voltage for Low-Voltage Differential Signaling (LVDS) |
N/A 1.250 V |
Maximum Offset Voltage for Low-Voltage Differential Signaling (LVDS) |
N/A 1.375 V |
Vibration |
N/A
Conditions MIL-STD-202 Method 214, Cond II-A Description 0.2 PSD, 6.21 gRMS |
Shock |
N/A
Conditions MIL-STD-202 Method 213, Cond C Description 100 g, 11 ms duration, half-sine |
Fine Leak |
N/A
Conditions MIL-STD-202 Method 213, Cond C |
Terminal Finish |
N/A Gold plated (E) is standard. SnPb 63/37 (PB) and SnAg (LF) also available |
Package Weight |
N/A 0.5 g |
Soldering Instruction |
N/A Reflow |
Shipping |
N/A T and R Tray Pack |
Operating Temperature |
N/A -55 to 95 ºC |
Storage Temperature |
N/A -55 to 125 ºC |
Marking |
N/A
Line 1: Greenray logo Line 2: Model Line 3: Frequency Line 4: Serial Number + Date Code (YYWW) |
Applications |
N/A
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Features |
N/A
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